Read latency is increasingly a problem for semiconductor memories operated at high frequency. Particularly for fast network memories intended to act, by way of example, for the purpose of temporary buffer-storage of a 10 Gbit/s data stream over a few milliseconds, semiconductor memories in which data are output as closely as possible to the time of the read command are required. The read latency, which represents the period of time which elapses between the read command and the first data bit on the data bus, is comparatively high, particularly in the case of DRAM memory architectures. Buffer-stores used for a network processor unit (NPU) are therefore often SRAM memory chips, which have relatively low read latency. However, such SRAM memory chips have the drawback that they cannot be produced using very large scale integration and are therefore comparatively expensive.